Compute performance is reaching a plateau. As electrical interconnects approach their limits, gains in processors such as GPUs and memory are also slowing because silicon transistor density can no longer improve at its historical rate. Future manufacturing advances will still raise chip and memory performance, but only incrementally compared with the exponential gains of the past.
Interconnect performance becomes the system-level differentiator. With traditional compute components reaching maturity, future AI system performance will increasingly depend on how efficiently processors and memory exchange data. Staera Lightwire interconnect chips and boards are designed to remove that constraint—and help set the pace of AI.
AI hardware has a new bottleneck, and it’s not the chips. It's the interconnections between them. Staera removes that bottleneck by carrying data on light instead of electricity, with the light emitters, waveguides and detectors built directly into a silicon chip.
For decades, compute performance came from making individual chips more powerful and efficient – Moore’s Law. That curve has flattened.
AI systems now scale by connecting more chips together: processors to memory, processors to each other, packages to packages. The whole system hangs on how fast, how far and how efficiently those chips can talk to each other.
That is exactly where electrical interconnects struggle. Electrical performance falls off sharply between one millimeter and one meter, the range where AI hardware moves the most data. Chips can only talk efficiently to their nearest neighbors. Memory has to sit at the edge of the processor. System architects end up designing around interconnect limits rather than optimizing for the needs of the workload.
Light doesn’t lose performance over distance the way electricity does, which is why optical fiber carries nearly all long-haul data today. But light has stalled at the edge of the package that carries chips, and the reason is heat.
Inside a package, cooling is the hard constraint. Power efficiency, not raw interconnect speed, sets how much data you can really move. The industry is miniaturizing optical fibers systems, calling them co-packaged optics (CPO). CPO is great for getting to and from the package, but their 5 pJ/bit efficiency is far too hot to move data inside the package. So, the last meter, from the chip across the package through the rack unit, is still electrical despite its limitations.
Staera makes light a native part of silicon. Three technologies, one wafer-level process:
• Silicon CMOS for drivers, receivers, photodetectors and control logic
• GaN LEDs as compact, efficient on-chip light emitters
• Silicon nitride waveguides to route light across the chip
These are not separate components assembled together. We build them monolithically, with the silicon on top: an optical backplane sits beneath a working silicon chip, fabricated and self-aligned together in the same process.
That architecture is the whole trick. The silicon layer's metal contacts stay on top, where processors and memory attach to them directly. The light emitters and detectors sit close to the silicon, so there is very little capacitance between them, which makes the receivers especially efficient. And because the optics are built with the chip rather than added afterward, they inherit silicon's reliability, density and yield.
Our first product on this platform is Lightwire.
AI hardware today is built on 2.5D packaging, where AI chips are connected by a third chip, a silicon bridge or interposer chip. Lightwire builds a fully-integrated optical backplane into that bridge chip, which drops into 2.5D packaging physically and electrically.
The numbers are what make it work inside the package:
• 4–8 Gbps per link, with more than 600 links per millimeter of chip edge
• Below 0.2 pJ/bit by design, a fraction of the energy of conventional optical solutions
• More than 100x the net performance of electrical across the millimeter-to-meter range
Those gains change what a package can do. HBM4 delivers 2.8 TB/s per stack today; Lightwire-based HBM is designed to exceed 24 TB/s. A UCIe-A die-to-die link stops at 2 mm; Lightwire reaches past 50 mm. At 24 TB/s of memory bandwidth, co-packaged optics at 5 pJ/bit would draw nearly 1 kW, while Lightwire at 0.2 pJ/bit draws under 40 W.
Lasers are unbeatable for speed and reach over optical fiber. Inside a package, heat is the limiting constraint.
To amortize their power, laser interconnects have to run very fast, which means extensive serializer/deserializer (SerDes) circuitry. Lightwire runs near the speed of on-chip data instead, with massively parallel interconnects, so they have much less overhead. Lightwire light is also absorbed within a very short distance in silicon, which allows very small photodetectors with around 5 fF of capacitance.
Lasers carry data off the package over fiber. Lightwire carries it within and across the package.
A new interconnect only matters if it can be made at scale.
Staera's process is designed for commercial silicon foundries and stays compatible with existing equipment and process flows.
Staera has built GaN LEDs into silicon chips in commercial foundries since 2016, perfecting the process to run at 98–99% yield over the past two years. Our platform was built over a decade with more than $100 million of funding through the Singapore-MIT Alliance for Research and Technology, and is protected by 86 granted patents worldwide.
Lightwire is built on mature 28–65 nm silicon processes, keeping development affordable and production scaling practical. We integrate our revolutionary GaN emitters and waveguides into commercial silicon CMOS PDKs, enabling designers to design new chips in standard EDA tools.
Lightwire doesn't replace processors or memory. It makes them better. They can run faster or cooler. Systems can connect across bigger chips and between more of them. And because Lightwire is made in silicon foundries and drops into today's 2.5D packaging, it fits the way the industry already builds AI hardware.
Smaller. Cooler. Faster. The next generation of compute doesn't have to be bigger than the last to be better than it.